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| Datasheet File OCR Text: |
| geometry process details principal device types czt127 cjd127 gross die per 4 inch wafer 1,445 process CP630 power transistor pnp - silicon darlington transistor chip process epitaxial planar die size 80 x 80 mils die thickness 8.0 mils base bonding pad area 18 x 27 mils emitter bonding pad area 34 x 34 mils top side metalization al - 30,000? back side metalization ti/pd/ag - 20,000? www.centralsemi.com r2 (22-march 2010)
process CP630 typical electrical characteristics www.centralsemi.com r2 (22-march 2010) |
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